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low capacitance, low charge injection, 15 v/12 v i cmos spdt in sot-23 ADG1219 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. ADG1219 decoder sa in en sb features <0.5 pc charge injection over full signal range 2.5 pf off capacitance low leakage; 0.6 na maximum @ 85c 120 on resistance fully specified at +12 v, 15 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 8-lead sot-23 package applications automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems audio/video signal routing communication systems functional block diagram d 06575-001 switches shown fo r a logic 0 input 0.5 ?0.5 ?15 15 06575-033 input voltage (v) charge injection (pc) figure 1. general description the ADG1219 is a monolithic i cmos? device containing an spdt switch. an en input is us ed to enable or disable the device. when disabled, all channels are switched off. when on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. each switch exhibits break-before-make switching action. the i cmos (industrial cmos) modular manufacturing process combines high voltage complementary metal-oxide semiconductor (cmos) and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no other generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased perfor- mance, dramatically lower power consumption, and reduced package size. the ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisi- tion and sample-and-hold applications, where low glitch and fast settling are required. figure 2 shows that there is minimum charge injection over the entire signal range of the device. i cmos construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. t a = 25oc 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v ?10 ?5 0 5 10 figure 2. charge injection vs. input voltage
ADG1219 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 4 ? absolute maximum ratings ............................................................6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? typical performance characteristics ..............................................8 ? test circuits ..................................................................................... 12 ? terminology .................................................................................... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 3/09rev. 0 to rev. a change to power requirements, i dd parameter, table 1 .............. 4 change to power requirements, i dd parameter, table 2 .............. 5 updated outline dimensions ........................................................ 15 4/08revision 0: initial version
ADG1219 rev. a | page 3 of 16 specifications dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. b version 1 parameters 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 120 typ v s = 10 v, i s = ?1 ma; see figure 23 200 240 270 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels, ?r on 3.5 typ v s = 10 v, i s = ?1 ma 6 10 12 max on resistance flatness, r flat(on) 20 typ v s = ?5 v, 0 v, +5 v; i s = ?1 ma 64 76 84 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.004 na typ v s = 10 v, v s = 10 v; see figure 24 0.1 0.6 1 na max drain off leakage, i d (off) 0.009 na typ v s = 10 v, v s = 10 v; see figure 24 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 10 v; see figure 25 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 transition time, t transition 140 ns typ r l = 300 , c l = 35 pf 170 200 230 ns max v s = 10 v; see figure 30 t on (en) 85 ns typ r l = 300 , c l = 35 pf 105 130 140 ns max v s = 10 v; see figure 30 t off (en) 105 ns typ r l = 300 , c l = 35 pf 125 150 170 ns max v s = 10 v; see figure 30 break-before-make time delay, t bbm 40 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 31 charge injection 0.1 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 77 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz ?3 db bandwidth 520 mhz typ r l = 50 , c l = 5 pf; see figure 28 c s (off) 2.5 pf typ f = 1 mhz; v s = 0 v 3.3 pf max f = 1 mhz; v s = 0 v c d (off) 4.3 pf typ f = 1 mhz; v s = 0 v 5.1 pf max f = 1 mhz; v s = 0 v c d , c s (on) 7.5 pf typ f = 1 mhz; v s = 0 v 10 pf max f = 1 mhz; v s = 0 v
ADG1219 rev. a | page 4 of 16 b version 1 parameters 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 140 a typ digital inputs = 5 v 190 a max i ss 0.001 a typ digital inputs = 0 v, 5 v or v dd 1.0 a max v dd /v ss 5/16.5 v min/max |v dd | = |v ss | 1 temperature range for b version is ?40c to +125c. 2 guaranteed by design; not subject to production test. single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. b version 1 parameters 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 300 typ v s = 0 v to 10 v, i s = ?1 ma; see figure 23 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels, ?r on 4.5 typ v s = 0 v to 10 v, i s = ?1 ma 16 26 27 max on resistance flatness, r flat(on) 60 typ v s = 3 v, 6 v, 9 v, i s = ?1 ma leakage currents v dd = 13.2 v source off leakage, i s (off) 0.006 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 24 0.1 0.6 1 na max drain off leakage, i d (off) 0.006 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 24 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 1 v or 10 v; see figure 25 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 2 transition time, t transition 195 ns typ r l = 300 , c l = 35 pf 250 300 340 ns max v s = 8 v; see figure 30 t on (en) 120 ns typ r l = 300 , c l = 35 pf 150 190 210 ns max v s = 8 v; see figure 30 t off (en) 145 ns typ r l = 300 , c l = 35 pf 185 220 255 ns max v s = 8 v; see figure 30 break-before-make time delay, t bbm 70 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 8 v; see figure 31 charge injection ?0.8 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 ?3 db bandwidth 400 mhz typ r l = 50 , c l = 5 pf; see figure 28
ADG1219 rev. a | page 5 of 16 b version 1 parameters 25c ?40c to +85c ?40c to +125c unit test conditions/comments c s (off) 2.9 pf typ f = 1 mhz; v s = 6 v 3.7 pf max f = 1 mhz; v s = 6 v c d (off) 5 pf typ f = 1 mhz; v s = 6 v 5.8 pf max f = 1 mhz; v s = 6 v c d , c s (on) 8.5 pf typ f = 1 mhz; v s = 6 v 11 pf max f = 1 mhz; v s = 6 v power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 140 a typ digital inputs = 5 v 190 a max v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v 1 temperature range for b version is ?40c to +125c. 2 guaranteed by design; not subject to production test.
ADG1219 rev. a | page 6 of 1 6 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current per channel, s or d 30 ma operating temperature range industrial (b version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 8-lead sot-23, ja thermal impedance 211.5c/w reflow soldering peak temperature, pb free 260c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADG1219 rev. a | page 7 of 16 06575-00 pin configuration and fu nction descriptions 3 en 1 v dd 2 gnd 3 v ss 4 in 8 sa 7 d 6 sb 5 nc = no connect ADG1219 top view (not to scale) figure 3. sot-23 pin configuration table 4. pin function descriptions pin no. mnemonic description 1 en active high digital input. when this pin is low, th e device is disabled and all switches are turned off. when this pin is high, the in logic in put determines which switch is turned on. 2 v dd most positive power supply potential. 3 gnd ground (0 v) reference. 4 v ss most negative power supply potential. 5 sb source terminal. can be an input or output. 6 d drain terminal. can be an input or output. 7 sa source terminal. can be an input or output. 8 in logic control input. table 5. truth table en in switch a switch b 0 x off off 1 0 on off 1 1 off on
ADG1219 rev. a | page 8 of 16 source or drain voltage (v) 0 ?18 ?15 ?12 ?9 ?6 ?3 12 15 9 06 31 8 typical performance characteristics on resistance ( ? ) 200 100 06575-004 180 160 140 120 80 60 40 20 t a = 25c v dd = 15v v ss = ?15v v dd = 16.5v v ss = ?16.5v v dd = 13.5v v ss = ?13.5v figure 4. on resistance as a function of v d (v s ) for dual supply temperature (c) on resistance ( ? ) 250 0 ?15 ?10 ?5 10 05 15 06575-007 v dd = 15v v ss = ?15v 150 200 100 50 t a = +125c t a = +85c t a = +25c t a = ?40c figure 7. on resistance as a function of v d (v s ) for different temperatures, dual supply source or drain voltage (v) 0 ?6 ?4 ?2 4 02 6 on resistance ( ? ) 600 300 06575-005 500 400 200 100 t a = 25c v dd = 5v v ss = ?5v v dd = 5.5v v ss = ?5.5v v dd = 4.5v v ss = ?4.5v figure 5. on resistance as a function of v d (v s ) for dual supply temperature (c) on resistance ( ? ) 600 0 024 10 68 12 06575-008 v dd = 12v v ss = 0v t a = +125c 300 400 200 500 100 t a = +85c t a = +25c t a = ?40c figure 8. on resistance as a function of v d (v s ) for different temperatures, single supply source or drain voltage (v) 0 02 46 12 810 14 on resistance ( ? ) 450 250 300 06575-006 400 350 150 200 100 50 t a = 25c v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v v dd = 10.8v v ss = 0v figure 6. on resistance as a function of v d (v s ) for single supply 0.6 ?1.0 0 06575-030 leakage (na) v dd = 15v v ss = ?15v v bias = +10v/?10v temperature (c) 20 40 60 80 100 120 i s (off)+? i d (off)+? i s (off)?+ i d (off)?+ i d , i s (on)++ i d , i s (on)? ? 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 figure 9. leakage currents as a function of temperature, 15 v dual supply
ADG1219 rev. a | page 9 of 16 0.6 ?0.3 0 06575-031 leakage (na) temperature (c) 20 40 60 80 100 120 i s (off)+? i d (off)+? i s (off)?+ i d (off)?+ i d , i s (on)++ i d , i s (on)? ? v dd = 12v v ss = 0v v bias = 1v/10v 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 figure 10. leakage currents as a function of temperature, 12 v single supply 0.3 ?0.5 0 06575-032 leakage (na) temperature (c) 20 40 60 80 100 120 i s (off)+? i d (off)+? i s (off)?+ i d (off)?+ i d , i s (on)++ i d , i s (on)? ? 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 5v v ss = ?5v v bias = +4.5v/?4.5v figure 11. leakage currents as a function of temperature, 5 v dual supply logic, in x (v) 20 0 0 2 4 6 8 10121416 i dd (a) 200 60 80 100 120 140 160 180 40 v dd = +12v v ss = 0v v dd = +15v v ss = ?15v i dd per channel t a = 25 c 06575-009 0.5 ?0.5 ?15 15 06574-041 input voltage (v) charge injection (pc) figure 12. i dd vs. logic level t a = 25oc 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 v dd = +15v v ss = ?15v v dd = 12v v ss = 0v v dd = +5v v ss = ?5v ?10 ?5 0 5 10 figure 13. charge injection vs. input voltage 300 0 ?40 ?20 0 120 1008060 40 20 06575-027 temperature (oc) time (ns) 250 200 150 100 50 15v ds 12v ss 0 6575-022 isolation (db) figure 14. t transition time vs. temperature ?110 10k 1g 0 frequency (hz) 100k 1m 10m 100m ?10 ?20 ?30 ?40 ?50 ?60 ?80 ?70 ?90 ?100 v dd = 15v v ss = ?15v t a = 25oc figure 15. off isol ation vs. frequency
ADG1219 rev. a | page 10 of ?110 ?100 10k 1g 06575-026 100k 1m 10m 100m 16 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 crosstalk (db) frequency (hz) v dd = 15v v ss = ?15v t a = 25oc figure 16. crosstalk vs. frequency 0 insertion loss (db) 8 0 ?15 15 06575-023 source voltage (v) capacitance (pf) ?14 10k 1g 06575-021 frequency (hz) 100k 1m 10m 100m ?2 ?4 ?6 ?8 ?10 ?12 v dd = 15v v ss = ?15v t a = 25oc figure 17. on response vs. frequency frequency (hz) 0.01 10 100 1k 10k 100k 06575-010 thd + n (%) 10.00 1.00 0.10 load = 10k ? t a = 25c v dd = 5v, v ss = ?5v, v s = 3.5v rms v dd = 15v, v ss = ?15v, v s = 5v rms figure 18. thd + n vs. frequency 7 6 5 4 3 2 1 source/drain on drain off source off ?10 ?5 0 5 10 v dd = 15v v ss = ?15v t a = 25oc 9 0 01 2 06575-024 source voltage (v) capacitance (pf) figure 19. capacitance vs. source voltage for dual supply 8 7 6 5 4 3 2 1 source/drain on drain off source off 246810 v dd = 12v v ss = 0v t a = 25oc 10 9 0 06575-025 capacitance (pf) 8 7 6 5 4 3 2 1 figure 20. capacitance vs. source voltage for single supply ?5 5 source voltage (v) ?3 ?1 1 3 source/drain on drain off source off v dd = 5v v ss = ?5v t a = 25oc figure 21. capacitance vs. source voltage for dual supply
ADG1219 rev. a | page 11 of 1 6 ?100 100k 1m 10m 06575-03 frequency (hz) 0 4 acpsrr (db) 100m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 v dd = +15v v ss = ?15v v p-p = 0.63v t a = 25c decoupling caps on no decoupling caps on figure 22. acpsrr vs. frequency
ADG1219 rev. a | page 12 of 1 6 test circuits i ds v s sd 06575-011 v figure 23. on resistance sd v v s a a v d i s (off) i d (off) 06575-012 figure 24. off leakage sd a v d i d (on) nc nc = no connect 06575-013 figure 25. on leakage v out 50 ? network analyzer r l 50? in v in sa d v s v dd v ss 0.1f v dd 0.1f v ss gnd 06575-017 50 ? nc sb off isolation = 20 log v out v s figure 26. off isolation v out 50? network analyzer r l 50? in v in sa d v s v dd v ss 0.1f dd 0.1f v ss gnd 06575-018 50? nc sb insertion loss = 20 log v out with switch v out without switch figure 27. channel-to-channel crosstalk v channel-to-channel crosstalk = 20 log v out gnd sa d sb v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f dd 0.1f v ss 06575-019 in figure 28. bandwidth v v out r s audio precision r l 10k? in v in s d v s v p-p v dd v ss 0.1f dd 0.1f v ss gnd 06575- 020 figure 29. thd + noise
ADG1219 rev. a | page 13 of 1 6 06575-014 in v out v v dd ss d sa v dd v ss gnd c l 35pf sb v v s in 0.1f 0.1f r l 300 ? v in v out v in 50% 50% 90% 50% 50% 90% t on t off figure 30. switching times 06575-015 in v out v dd v ss d sa v dd v ss gnd c l 35pf sb v v s in 0.1f 0.1f 80% t bbm t bbm v out v in r l 300 ? figure 31. break-before-make time delay v in (normally closed switch) v out v in (normally open switch) off v out on q inj = c l v out 06575-016 in v out v v dd ss d sa v dd v ss gnd c l 1nf nc sb v in v s 0.1f 0.1f figure 32. charge injection
ADG1219 rev. a | page 14 of 1 6 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, measured with reference to ground. c d (off) the off switch drain capacitance, measured with reference to ground. c d , c s (on) the on switch capacitance, measured with reference to ground. c in the digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% point of both switches when switching from one a ddress state to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. total harmonic distortion (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. ac power supply rejection ratio (acpsrr) measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
ADG1219 rev. a | page 15 of 1 6 outline dimensions compliant to jedec standards mo-178-ba 121608-a 8 4 0 seating plane 3.00 2.90 2.80 76 1234 5 1.95 bsc 0.65 bsc 0.60 bsc 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.22 max 0.08 min 0.38 max 0.22 min 0.60 0.45 0.30 pin 1 indicator 8 figure 33. 8-lead lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADG1219brjz-r2 1 ?40c to +125c 8-lead lead small outlin e transistor package [sot-23] rj-8 s24 ADG1219brjz-reel7 1 ?40c to +125c 8-lead lead small outlin e transistor package [sot-23] rj-8 s24 1 z = rohs compliant part.
ADG1219 rev. a | page 16 of 16 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06575-0-3/09(a)

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